Explain how to use the make command under linux

In this article, we will use a few examples to discuss the working mechanism behind the make command.

How does Make work
For those who don't know the mechanics behind it, the make command receives the target like the command-line argument 1. These targets are usually stored in special files named "Makefile," which also contain actions corresponding to the target. For more information, read a series of articles about how Makefiles works.

When the make command is executed the first time, it scans Makefile to find the target and its dependencies. If the dependencies are themselves targets, continue to scan Makefile for the dependencies to establish their dependencies, and then compile them. Once the master dependency is compiled, the master target is compiled (this is passed in via the make command).

Now, if you make a change to a source file and you execute make again, it will compile only the target file associated with the source file, thus saving a lot of time by compiling the final executable.

Make command instance
Here is the test environment used in this article:

OS  -  Ubunut 13.04
Shell  -  Bash 4.2.45
Application  -  GNU Make 3.81

Here's what the project looks like:

$ ls 
anotherTest.c Makefile test.c test.h

Here's what Makefile says:

all: test 

test: test.o anotherTest.o 
  gcc -Wall test.o anotherTest.o -o test

test.o: test.c 
  gcc -c -Wall test.c 

anotherTest.o: anotherTest.c 
  gcc -c -Wall anotherTest.c 

clean: 
  rm -rf *.o test

Now let's take a look at some examples of Linux in action:

1. A simple example

To compile the entire project, you can simply use make or bring the target all after the make command.

$ make 
gcc -c -Wall test.c 
gcc -c -Wall anotherTest.c 
gcc -Wall test.o anotherTest.o -o test

You can see the dependency created the first time with the make command and the actual target.

If you look at the contents of the directory again, there are more.o files and executable files:

$ ls 
anotherTest.c anotherTest.o Makefile test test.c test.h test.o

Now, suppose you made some changes to the test.c file and recompiled the project using make:

$ make 
gcc -c -Wall test.c 
gcc -Wall test.o anotherTest.o -o test

You can see that only test.o has been recompiled, while the other Test.o has not been recompiled.

Now clean up all the target files and the executable test, you can use the target clean:

$ make clean
rm -rf *.o test

$ ls
anotherTest.c Makefile test.c test.h

You can see that all the.o files and the test execution files have been deleted.

2. Always reset all targets with the -B option

So far, you may have noticed that the make command does not compile files that have not changed since the last build, but if you want to override the default behavior of make, you can use the -B option.

Here's an example:

$ make
make: Nothing to be done for `all'.

$ make -B
gcc -c -Wall test.c
gcc -c -Wall anotherTest.c
gcc -Wall test.o anotherTest.o -o test

You can see that while the make command does not compile any files, make-B forces all target files to be compiled, as well as the final execution files.

3. Print debugging information using the -d option

If you want to know what make actually does when it executes, use the -d option.

Here's an example:

$ make -d | more
GNU Make 3.81
Copyright (C) 2006 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.

This program built for x86_64-pc-linux-gnu
Reading makefiles ... 
Reading makefile `Makefile' ... 
Updating makefiles ... .
Considering target file `Makefile'.
Looking for an implicit rule for `Makefile'.
Trying pattern rule with stem `Makefile'.
Trying implicit prerequisite `Makefile.o'.
Trying pattern rule with stem `Makefile'.
Trying implicit prerequisite `Makefile.c'.
Trying pattern rule with stem `Makefile'.
Trying implicit prerequisite `Makefile.cc'.
Trying pattern rule with stem `Makefile'.
Trying implicit prerequisite `Makefile.C'.
Trying pattern rule with stem `Makefile'.
Trying implicit prerequisite `Makefile.cpp'.
Trying pattern rule with stem `Makefile'.
--More--

This is a long output, and you can see that I used the more command to display the output page by page.

4. Change the directory using the -C option

You can provide a different directory path for the make command and switch directories before looking for Makefile.

This is a directory, assuming you are in the current directory:

$ ls 
file file2 frnd frnd1.cpp log1.txt log3.txt log5.txt
file1 file name with spaces frnd1 frnd.cpp log2.txt log4.txt

But the make file you want to run for the make command is saved in.. / make-dir/directory, you can do this:

$ ls 
anotherTest.c Makefile test.c test.h

0

You can see that the make command first cuts to a particular directory, executes there, and then switches back.

5. View other files as Makefile with the -f option

If you want to rename the Makefile file, such as my_makefile or some other name, we want make to use it as Makefile as well, using the -f option.

$ ls 
anotherTest.c Makefile test.c test.h

1

In this way, the make command chooses to scan my_makefile instead of Makefile.

The above is the detailed content of this article, I hope to help you with your study.